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RT9725A/b 1 ds9725a/b-01 april 2011 www.richtek.com ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. express card power interface switch general description the RT9725A/b power distribution switches are designed to fulfill power management requirements of express card specification. the RT9725A/b supports systems with single slot expresscard|34 and expresscard|54 socket. the device distributes 3.3v, aux and 1.5v to the express card socket. each power rail is protected with current limit circuitry when output load exceeds over-current threshold or short-circuits occurs. a thermal protection circuit turns off switches to prevent the device from damage when power dissipation is increased by continuous heavy overloads or short-circuits in the switches. the RT9725A/b is available in wqfn-20l 3x3 package. applications z pcs z pdas z digital cameras z tv and set top boxes marking information for marking information, contact our sales representative directly or through a richtek distributor located in your area. features z z z z z meets express card standard (expresscard|34 and expresscard|54) z z z z z compliant with the express card compliance check lists, compliance id : ec100328 z z z z z fully satisfy the express card implementation guidelines z z z z z supports systems with wake function z z z z z ttl-logic compatible input z z z z z under-voltage lockout protection z z z z z over current protection z z z z z over temperature protection z z z z z rohs compliant and halogen free pin configurations (top view) wqfn-20l 3x3 gnd auxout 3.3vin 3.3vout nc nc 1.5vout 1.5vin nc nc nc auxin rclken 1 2 3 4 67 8 9 15 14 13 12 17 20 18 19 21 gnd 5 11 10 16 stby shdn flg sysrst perst cppe cpusb package type qw : wqfn-20l 3x3 (w-type) RT9725A/b lead plating system g : green (halogen free and pb free) sysrst pull high resistor a : with internal resistor b : without internal resistor
RT9725A/b 2 ds9725a/b-01 april 2011 www.richtek.com pin no. pin name pin function 1 stby standby input-active low, logic level signal, internal pulled up to auxin. 2 3.3vin input pin for 3.3v output voltage. 3 3.3vout switched output that delivers 0v,3.3v or high impedance to card. 4, 5, 13, 14, 16 nc no internal c onnection. 6 sysr st system reset input-active low, logic level signal, internal pulled up to auxin for RT9725A or floating for rt9725b. 7, 21 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. 8 perst a logic level power good to slot (with delay). 9 cpu sb card present input for usb cards, internal pulled up to au xin. 10 cppe card present input for pci cards, internal pulled up to auxin. 11 1.5vout switched output that delivers 0v,1.5v or high impedance to card. 12 1.5vin input pin for 1.5v output voltage. 15 auxout switched output that delivers 0v,aux or high impedance to card. 17 auxin aux inp ut fo r au xout an d chip po wer. 18 rclken reference clock enable signal. as an out put, a logic power good to host for slot (no delay-open drain). as an input, if kept inactive(low) by the host, prevents perst from being de-asserted. internal pulled up to auxin 19 flg over current or over temperature status output for slot (open drain) 20 shd n shutdown input-active low, logic level signal. internal pulled up to auxin functional pin description typical application circuit r t 9 7 2 5 a / b 3.3vin 3.3vout gnd rclken auxin auxout 1.5vin 1.5vout sysrst shdn stby perst cppe cpusb flg 2 2 f 2 2 f 3.3v 3.3v 1.5v sysrst shdn stby flg 3.3vout auxout 1.5vout perst cppe cpusb rclken 4 . 7 f 4 . 7 f 4 . 7 f 2 2 f 1 0 0 k 1 2 3 6 7, exposed pad (21) 8 9 15 12 17 20 18 19 11 10
RT9725A/b 3 ds9725a/b-01 april 2011 www.richtek.com function block diagram current limit current limit current limit power good gate control auxin delay otp uvlo charge pump oscillator 3.3vin 3.3vout gnd rclken auxin auxout 1.5vin 1.5vout sysrst shdn stby perst cppe cpusb flg auxin RT9725A only
RT9725A/b 4 ds9725a/b-01 april 2011 www.richtek.com operation table 1. truth table for voltage outputs input power (1) logic input output (2) auxin 3.3vin 1.5vin shdn stby cpxx (4) auxout 3.3vout 1.5vout mode (3) off x x x x x off off off off on x x 0 x x gnd gnd gnd shutdown on x x 1 x 1 gnd gnd gnd no card on off 1 1 1 >> 0 off off off off on on >> off 1 1 0 on off off standby (5) on on on 1 0 0 on off off standby on on on 1 1 0 on on on card inserted table 2. truth table for logic output input conditions logic outputs mode sysrst rclken (1) perst rclken (2) off x x 0 0 shutdown no card sta ndb y card inserted 0 h i-z 0 1 0 0 0 0 1 h i-z 1 1 1 0 0 0 (1) for power input : ? on ? means the respective input voltage is higher than its turn on threshold voltage; ? off ? means the input voltage is lower than its uvlo falling threshold voltage. (for aux input, ? off ? means the voltage is close to 0v). (2) for output : ? on ? means the respective power switch is turned on, so that the input is connected to the output; ? off ? means the power switch and its output discharge fet are both off; ? gnd ? means the powers switch is off but the output discharge fet is on, so that the voltage on the output is pulled down to 0v. (3) mode assigns each set of input conditions and respective output voltage results to a different name. these modes are referred to as input conditions in the following ? truth table ? for logic outputs. (4) cpxx = 1 when both cpusb and cppe signals are logic high, or cpxx = 0 when either cpusb or cppe is low. (5) the card is inserted prior to the removal of the primary or secondary power (either 3.3vin or 1.5vin or both) at the input of the expresscard power switch, then only the primary and secondary power (both 3.3vout and 1.5vout) are removed and the auxiliary power is sent to the expresscard slot. (6) ? x ? means ? don'st care ? . (1) rclken acts as a logic input in this column. rclken is an i/o pin and it can be driven low externally, left open, or connected to high-impedance terminals, such as the gate of a mosfet. it must not be driven high externally. (2) rclken acts as a logic output in this column.
RT9725A/b 5 ds9725a/b-01 april 2011 www.richtek.com electrical characteristics to be continued recommended operating conditions (note 4) z supply voltage (auxin, 3.3vin) ----------------------------------------------------------------------------------- 3v to 3.6v z supply voltage (1.5vin) --------------------------------------------------------------------------------------------- 1.35v to 1. 65v z junction temperature range ---------------------------------------------------------------------------------------- ? 40 c to 100 c z ambient temperature range ---------------------------------------------------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) z supply voltage (auxin, 3.3vin) ----------------------------------------------------------------------------------- ? 0.3v to 5v z supply voltage 1.5vin ----------------------------------------------------------------------------------------------- ? 0.3v to 2.5v z logic input/output voltage ------------------------------------------------------------------------------------------ ? 0.3v to 5v z power dissipation, p d @ t a = 25 c wqfn-20l 3x3 -------------------------------------------------------------------------------------------------------- 1.667w z package thermal resistance (note 2) wqfn-20l 3x3, ja --------------------------------------------------------------------------------------------------- 60 c/w wqfn-20l 3x3, jc -------------------------------------------------------------------------------------------------- 7.5 c/w z junction temperature ------------------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 se c.) --------------------------------------------------------------------------- 260 c z storage temperature range ---------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ------------------------------------------------------------------------------------------ 2kv mm (ma chine mode) -------------------------------------------------------------------------------------------------- 200v parameter symbol test conditions min typ max unit power switch r ds(on)_33 3.3vin to 3.3vout, i out = 1300ma -- 90 120 r ds(on)_15 1.5vin to 1.5vout, i out = 650ma -- 90 120 switch on resistance r ds(on)_aux auxin to auxout, i out = 275ma -- 120 160 m discharge resistance (3.3v/1.5v/aux output) r discharge v shdn = 0v, i discharge = 1ma 100 300 500 i sc _33 1350 2000 2500 i sc _15 670 1000 1300 output short-circuit current (steady state value) i sc _aux output power into a short 275 450 600 ma i q_33 -- 25 30 i q_15 -- 25 30 total input quiescent current (normal operation) i q _aux output are unloaded (include cppe and cpusb logic pull-up current) -- 250 280 a i shdn_33 -- 5 10 i shdn_15 -- 5 10 total input quiescent current (shutdown mode) i shdn _aux v cppe = v cpusb = v shdn = 0v, discharge fets are on (include cppe, cpusb and shdn pull-up current) -- 280 310 a (v (3.3vin) = v (auxin) = 3.3v, v (1.5vin) = 1.5v, v shdn = v stby = v sysrst =3.3v, v cppe = v cpusb = 0v, perst, flg, rclken are open, all output voltage are unloaded; t a = 25 c, unless otherwise specified)
RT9725A/b 6 ds9725a/b-01 april 2011 www.richtek.com parameter symbol test c onditions min typ max u nit power sw itch i lkf_33 -- 0.1 50 i lkf_15 -- 0.1 50 forward leakage current i lkf _aux v cppe = v cpusb = v shdn = 3.3v, (no card present, discharge fets are on) current measured at input pins, include rclken pull-up current -- 20 50 a i lkr_33 -- 5 10 i lkr_15 -- 5 10 reverse leakage current i lkr _aux v 3.3vout = v auxvout = 3.3v, v 1.5vout = 1.5v, all voltage inputs are grounded (current measured from output pins going in) -- 5 10 a t sd rising temperature, not in over- current condition -- 130 -- t sd rising temperature, in over-current condition -- 100 -- thermal shutdown t sd hysteresis -- 20 -- c logic selection (shdn, stby, cppe, cpusb, sysrst, perst, flg, rclken v shdn = 3.3v, sinking -- 0 1 i shdn v shdn = 0v, sourcing -- 20 35 v stby = 3.3v, sinking -- 0 1 i stby v stby = 0v, sourcing -- 20 35 v cppe or v cpusb = 3.3v, sinking -- 0 1 i cppe or i cpusb v cppe or v cpusb = 0v, sourcing -- 20 35 v sysrst = 3.3v, s ink ing -- 0 1 i sysrst v sysrst = 0v, sourcing -- 20 35 logic input supply current i rclken v rclken = 0v, sourcing -- 20 35 a v ih high level 2 -- -- logic input voltage v il low level -- -- 0.8 v rclken output low voltage i rclken = 60ua -- 0.2 0.4 v v pgood_33 3.3vout falling 2.7 2.85 3 v pgood _15 1.5vout falling 1.2 1.27 1.35 perst assertion threshold of output voltage (perst asserted when any of outputs falls below the threshold) v pgood _aux auxout falling 2.7 2.85 3 v perst assertion delay from output voltage 3.3vout, auxout or 1.5vout falling -- 300 500 ns perst de-assertion delay from output voltage 3.3vout, auxout and 1.5vout rising within tolerance 4 10 20 ms perst assertion delay from sysrst maximum time from sysrst assertion -- -- 500 ns perst minimum pulse width 3.3vout, auxout or 1.5vout falling out of tolerance or triggered by sysrst 100 250 -- s high level, i perst = 500 a 2.4 -- -- perst output voltage low level, i perst = 500 a -- -- 0.4 v to be continued
RT9725A/b 7 ds9725a/b-01 april 2011 www.richtek.com parameter symbol test conditions min typ max unit flg output low voltage v flg i flg = 2ma -- 0.2 0.4 v flg leakage current i lk_flg v flg = 3.3v -- 0 1 a flg delay time t d falling into an over-current or over temperature condition 4 10 20 ms uvlo 3.3vin uvlo v u vlo_33 2.6 2.75 2.9 1.5vin uvlo v u vlo_15 below which 3.3vin and 1.5vin switches are off (rising vin) 1 1.125 1.25 auxin uvlo v u vlo_aux below which all switches are off (rising vin) 2.6 2.75 2.9 v hysteresis v uvlo falling vin -- 100 -- mv switching 3.3vin to 3.3vout, c 3.3vout = 0.1 f, i 3.3out = 0a 0.1 -- 3 t rise_33 3.3vin to 3.3vout, c 3.3vout = 100 f, r load_3.3 = v 3.3vin /1a 0.1 -- 6 1.5vin to 1.5vout, c 1.5vout = 0.1 f, i 1.5out = 0a 0.1 -- 3 t rise _15 1.5vin to 1.5vout, c 1.5vout = 100 f, r load_1.5 = v 1.5vin /0.5a 0.1 -- 6 auxin to auxout, c auxout = 0.1 f, i auxout = 0a 0.1 -- 3 output rising time t rise _aux auxin to auxout, c auxout = 100 f, r load_aux = v auxin /0.25a 0.1 -- 6 ms 3.3vin to 3.3vout, c 3.3vout = 0.1uf, i 3.3out = 0a 10 -- 150 s t fall_nc_33 3.3vin to 3.3vout, c 3.3vout = 20uf, i 3.3out = 0a 2 -- 30 ms 1.5vin to 1.5vout, c 1.5vout = 0.1 f, i 1.5out = 0a 10 -- 150 s t fall_nc _15 1.5vin to 1.5vout, c 1.5vout = 20 f, i 1.5out = 0a 2 -- 30 ms auxin to auxout, c auxou t = 0.1uf, i auxou t = 0a 10 -- 150 s output falling time when card removed (both cppe and cpusb de-asserted) t fall_nc _aux auxin to auxout, c auxou t = 20uf, i au xout = 0a 2 -- 30 ms 3.3vin to 3.3vout, c 3.3vout = 0.1 f, i 3.3out = 0a 10 -- 150 s t fall_sd_33 3.3vin to 3.3vout, c 3.3vout = 100uf, r load_3.3 = v 3.3vin /1a 0.1 -- 5 ms 1.5vin to 1.5vout, c 1.5vout = 0.1uf, i 1.5out = 0a 10 -- 150 s t fall_sd _15 1.5vin to 1.5vout, c 1.5vout = 100 f, r load_1.5 = v 1.5vin /0.5a 0.1 -- 5 ms auxin to auxout, c auxou t = 0.1 f, i auxout = 0a 10 -- 150 s output falling time when shdn asserted (card is present) t fall_sd _aux auxin to auxout, c auxout = 100 f, r load_aux = v auxin /0.25a 0.1 -- 5 ms
RT9725A/b 8 ds9725a/b-01 april 2011 www.richtek.com note 1. stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a high effective four layers thermal conductivity test board of jedec 51-7 thermal measurement standard. the case point of jc is on the expose pad for the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions.
RT9725A/b 9 ds9725a/b-01 april 2011 www.richtek.com typical operating characteristics when card inserted power on time (250 s/div) auxout (2v/div) 1.5vout (1v/div) 3.3vout (1v/div) cpusb /cppe (2v/div) power on time (2.5ms/div) rclken (2v/div) perst (2v/div) 3.3vout (2v/div) when power is on time (500ns/div) perst (2v/div) perst asserted by sysrst sysrst (2v/div) when card removed power off time (50 s/div) auxout (2v/div) rclken (2v/div) perst (2v/div) when auxin removed power off from auxin time (5ms/div) auxout (5v/div) auxin (5v/div) 1.5vout (2v/div) 3.3vout (5v/div) r l(3.3out) = 3.6 , r l(1.5out) = 2.7 , r l(auxout) = 12 , c l(3.3/1.5/auxout) = 68 f when power is on time (100 s/div) perst (2v/div) sysrst (2v/div) perst de-asserted by sysrst
RT9725A/b 10 ds9725a/b-01 april 2011 www.richtek.com 1.5v switch r ds(on) vs. output current 70 72 74 76 78 80 82 84 86 88 90 0.05 0.15 0.25 0.35 0.45 0.55 0.65 output current (a) r ds(on) (m ) (m ) 3.3v switch r ds(on) vs. output current 80 82 84 86 88 90 92 94 96 98 100 0 0.10.20.30.40.50.60.70.80.9 1 1.11.21.3 output current (a) r ds(on) (m [ ) (m ) time (5ms/div) i 3.3out (1a/div) flg response in 3.3vout short circuit flg (2v/div) when 1.5vin removed power off from 1.5vin time (500 s/div) r l(3.3out) = 3.6 , r l(1.5out) = 2.7 , r l(auxout) = 12 , c l(3.3/1.5/auxout) = 68 f auxout (5v/div) 1.5vin (2v/div) 1.5vout (2v/div) 3.3vout (5v/div) switch r ds(on) vs. temperature 50 60 70 80 90 100 110 120 130 140 150 160 170 -50 -25 0 25 50 75 100 temperature r ds(on) (m ) (m ) ( c) 1.5vin 3.3vin auxin i 1.5v = 0.65a, i 3.3v = 1.3a, i aux = 0.275a auxin switch r ds(on) vs. output current 110 115 120 125 130 135 140 25 50 75 100 125 150 175 200 225 250 275 output current (ma) r ds(on) (m ? ) (m )
RT9725A/b 11 ds9725a/b-01 april 2011 www.richtek.com auxin shutdown current vs. temperature 130 140 150 160 170 180 190 200 -50 -25 0 25 50 75 100 temperature shutdown current (ua) ( c) 3.3vin & 1.5vin shutdown current vs. temperature 0 2 4 6 8 10 12 14 16 18 20 -50 -25 0 25 50 75 100 temperature shutdown current (ua) ( c) 1.5vin 3.3vin 3.3vout current limit vs. temperature 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 -40 -20 0 20 40 60 80 temperature current limit (a) ( c) auxout current limit vs. temperature 0 0.1 0.2 0.3 0.4 0.5 0.6 -40-30-20-10 0 1020304050607080 temperature current limit (a) ( c) auxin quiescent current vs. temperature 150 160 170 180 190 200 210 220 -50 -25 0 25 50 75 100 temperature quiescent current (ua) ( c) no load 3.3vin & 1.5vin quiescent current vs. temperature 0 5 10 15 20 25 30 -50 -25 0 25 50 75 100 temperature quiescent current (ua) ( c) 1.5vin 3.3vin no load
RT9725A/b 12 ds9725a/b-01 april 2011 www.richtek.com 1.5vin uvlo threshold vs. temperature 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -40-20 0 20406080100 temperature uvlo threshold (v) ( c) rising falling 3.3vin uvlo threshold vs. temperature 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 -40 -20 0 20 40 60 80 100 temperature uvlo threshold (v) ( c) rising falling flg delay time vs. temperature 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 -40-20 0 20406080 temperature flg delay time (ms) ( c) auxin uvlo threshold vs. temperature 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 -40 -20 0 20 40 60 80 100 temperature uvlo threshold (v) ( c) rising falling 1.5vout current limit vs. temperature 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 -40 -20 0 20 40 60 80 temperature current limit (a) ( c)
RT9725A/b 13 ds9725a/b-01 april 2011 www.richtek.com the following conditions define the operation of the host power controller : 1. when both primary power and auxiliary power at the input of the expresscard power switch are off, then all power to the expresscard connector is off regardless of whether a card is present. 2. when both primary power and auxiliary power at the input of the expresscard power switch are on, then power is only applied to the expresscard after the expresscard power switch detects that a card is present. 3. when primary power (either +3.3 v or +1.5 v) at the input of the expresscard power switch is off and auxiliary power at the input of the expresscard power switch is on, then the expresscard power switch behaves in the following manner : a. if neither of the card present inputs is detected (no card inserted), then no power is applied to the expresscard slot. b. if the card is inserted after the system has entered this power state, then no power is applied to the expresscard slot. c. if the card is inserted prior to the removal of the primary power (either +3.3 v or +1.5 v or both) at the input of the expresscard power switch, then only the primary power (both +3.3 v and +1.5 v) is removed and the auxiliary power is sent to the expresscard slot. applications information power states off mode if auxin is not available, and then all input-to-output power switches will be kept off. shutdown mode if auxin is available and shdn is asserted (logic low), then all input-to-output power switches will be kept off and the output discharge fets will be turned on. if shdn is asserted and then de-asserted, the state on the output will be resumed to the state prior to shdn assertion. no card mode if 3.3vin, auxin and 1.5vin are all available at the input of the power switch and no card is inserted, then all input-to- output power switches will be kept off and the output discharge fets will be turned on. card inserted mode if 3.3vin, auxin and 1.5vin are available at the input of the power switch before a card is inserted, then all input- to-output power switches will be turned on once a card- present signal (cpusb and/or cppe) is detected. standby mode 1. if a card is existed and all output voltages are being applied, then the stby is asserted (logic low); the auxout voltage is provided to the card, and the 3.3vout and 1.5vout switches will be turned off. 2. if a card is existed and all output voltages are being applied, then the 1.5vin or 3.3vin is removed from the input of the power switch; the auxout voltage is provided to the card and the 3.3vout and 1.5vout switches will be turned off. expresscard power switch operation the expresscard power switch resides on the host, and its main function is to control when to send power to the expresscard slot. the expresscard power switch makes decisions based on the card present inputs and on the state of the host system as defined by the primary and auxiliary voltage rails.
RT9725A/b 14 ds9725a/b-01 april 2011 www.richtek.com express card timing diagrams host power (auxin / 3.3vin / 1.5vin) sysrst cpusb / cppe card power (auxout / 3.3vout / 1.5vout) rclken perst a b c d e figure 1. card present before host power host power (auxin / 3.3vin / 1.5vin) sysrst cpusb / cppe card power (auxout / 3.3vout / 1.5vout) rclken perst a b c host power (auxin) sysrst cpusb / cppe card power (auxout / 3.3vout / 1.5vout) rclken perst host power (3.3vin / 1.5vin) figure 2. host power is on prior to card insertion figure 3. host system in standby prior to card insertion tpd min max units a system dependent b -- 100 s c -- 10 ms d 100 -- s e -- 20 ms tpd min max units a -- 100 ms b -- 10 ms c -- 20 ms
RT9725A/b 15 ds9725a/b-01 april 2011 www.richtek.com figure 4. host controlled power down figure 5. controlled power down when shdn asserted figure 6. surprise card removal tpd min max units a system dependent b load dependent c -- 500 ns d -- 500 ns tpd min max units a system dependent b system dependent c load dependent d -- 500 ns e -- 500 ns tpd min max units a load dependent b -- 500 ns c -- 500 ns host power (auxin / 3.3vin / 1.5vin) sysrst cpusb / cppe card power (auxout / 3.3vout / 1.5vout) rclken perst a b c host power (auxin / 3.3vin / 1.5vin) cpusb / cppe card power (auxout / 3.3vout / 1.5vout) rclken perst a b c d e shdn host power (auxin / 3.3vin / 1.5vin) sysrst cpusb / cppe card power (auxout / 3.3vout / 1.5vout) rclken perst a b c d
RT9725A/b 16 ds9725a/b-01 april 2011 www.richtek.com thermal considerations for continuous operation, do not exceed absolute maximum operation junction temperature. the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = ( t j(max) ? t a ) / ja where t j(max) is the maximum operation junction temperature, t a is the ambient temperature and the ja is the junction to ambient thermal resistance. for recommended operating conditions specification of rt9725, the maximum junction temperature is 125 c. the junction to ambient thermal resistance ja is layout dependent. for wqfn-20l 3x3 packages, the thermal resistance ja is 60 c/w on the standard jedec 51-7 four layers thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula : p d(max) = (125 c ? 25 c) / (60 c/w) = 1.667w for wqfn-20l 3x3 the maximum power dissipation depends on operating ambient temperature for fixed t j(max) and thermal resistance ja . for rt9725 package, the figure 7 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power dissipation allowed. figure 7. derating curves for rt9725 package 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) wqfn -20 3x3 four layers pcb
RT9725A/b 17 ds9725a/b-01 april 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property infringemen t of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications is assumed b y richtek. richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com outline dimension d imensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 d 2.900 3.100 0.114 0.122 d2 1.650 1.750 0.065 0.069 e 2.900 3.100 0.114 0.122 e2 1.650 1.750 0.065 0.069 e 0.400 0.016 l 0.350 0.450 0.014 0.018 w-type 20l qfn 3x3 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2

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